1. Field of the Invention
The present invention relates to the field of connecting techniques for high frequency devices, and, more particularly, to a through connection for multi-layer printed circuit boards for high frequency applications.
2. Description of the Related Art
As semiconductor manufacturers continue to scale down on-chip features, the on-chip operating frequencies of those reduced size features may be accordingly increased, due substantially to reduced parasitic device capacitances. While, some applications, for example, state of the art microprocessors, may be driven with an on-chip operating frequency (clock rate) that may be higher than the input/output frequency, other applications, for example, high frequency transmitter and receiver devices, e.g., for wireless local area networks (WLANs) or mobile phones, may need to input/output high frequency signals in the GHz-range. For example, a WLAN transceiver may supply/receive a 2.4 GHz-signal to/from a connected antenna that may, for instance, be printed on a common substrate. Typically, integrated circuit die are mounted on a substrate and connected to other devices by conduction lines formed on an elaborate multi-layer substrate. In particular, connections for high frequency signals of more than 300 MHz are subjected to certain constraints with respect to the employed substrate materials and the line design and may be formed, for example, by microstrip lines to provide connection lines with a controlled impedance. Conventional through connections, however, may cause signal reflection and attenuation of high frequency signals, in particular in the GHz range.
On the other hand, as a general rule, scaled features enable increased functionality at a maintained die size, or a reduced die size at a maintained functionality. In both cases, however, the density of inputs and outputs (I/Os) on the die is increased. For a conventional peripheral bond pad arrangement, the resulting bond pad pitch (the distance between the centers of two adjacent bond pads) is accordingly reduced. Thus, bonding of die of advanced integrated circuits, in particular for high frequency integrated circuits, is a challenge for manufacturers of electronic components. Typically, integrated circuit devices are mounted on a substrate and the contact pads of the device are connected to corresponding pads on the substrate by wire bonding, tape automated bonding (TAB) or flip chip bonding techniques.
Contrary to wire bonding and TAB, flip chip bonding is not restricted to the employment of peripheral bond pads. The flip chip technology, however, requires an equal bump pitch on the die and on the substrate to which the die is to be bonded. The minimal bump pitch achievable on a substrate depends on the carrier material and on the corresponding available technology. In general, bond pad redistribution is required to provide reliable and cost-efficient components. Consequently, semiconductor manufacturers arrange the bond pads in two or more rows disposed in the peripheral region of the chip area (peripheral array), or redistribute the peripheral bond pads over the entire chip area (area array) to allow for a higher bond pad pitch. For high frequency integrated circuits, die with on-die redistribution of bump pads and chip carriers providing the required functionality are, in general, not available.
As a high frequency chip carrier material may be employed, for example, ceramic, polyimide or flame-retardant fiberglass epoxy laminate (FR4). In large-scale production, FR4 is, in spite of the poor material properties (high dielectric constant, high loss angle), even for high frequency applications, a widely used material for its economical benefits. Through connections formed with conventional FR4 printed circuit board (PCB) technologies, however, may cause undue high frequency signal deformation.
In view of the above-mentioned problems, there exists a need for an improved connection technique for devices in high frequency applications.